1. Field of the Invention
The present invention relates to a high breakdown voltage semiconductor device formed in a dielectrically isolated island, as well as a fabrication method thereof.
2. Description of the Background Art
FIG. 7 is a sectional view schematically depicting a structure of this type of conventional semiconductor device. Referring to FIG. 7, an n.sup.- -type semiconductor island 1 is surrounded by a low-resistance n.sup.+ -type semiconductor layer 2 and a dielectric layer 3. The n.sup.- -type semiconductor island 1 is supported by a polysilicon substrate 4, while the n.sup.- -type semiconductor island 1 and the n.sup.+ -type semiconductor layer 2 are insulated from the polysilicon substrate 4 by the dielectric layer 3.
Impurities are selectively diffused from the top surface of the n.sup.- -type semiconductor island 1 to form p-type diffusion regions 5, while impurities are selectively diffused from the surface of each p-type diffusion region 5 to form n.sup.+ -type diffusion regions 6. A polysilicon gate electrode 8 covered with an insulation film 7 is provided onto each end of the p-type diffusion regions 5, thereby forming a VDMOS transistor comprising a plurality of DMOS cells.
Impurities are also diffused from a center of the top surface of the n.sup.- -type semiconductor island 1 to form a deep n-type diffusion region 9 which extends from said surface and reaches the n.sup.+ -type semiconductor layer 2, while impurities are diffused from each end of the top surface of the n.sup.- -type semiconductor island 1 to form shallow n.sup.+ -type diffusion regions 10 which connect with the n.sup.+ -type semiconductor layer 2. Source electrodes 11 and drain electrodes 12 of aluminum are provided on the insulation film 7. The source electrodes 11 are electrically connected with the p-type diffusion regions 5 and the n.sup.+ -type diffusion regions 6 through contact holes provided upon the insulation film 7, while the drain electrodes 12 are electrically connected with the deep n-type diffusion region 9 of the island center and the shallow n.sup.+ -type diffusion regions 10 of the island edges through contact holes provided upon the insulation film 7.
When a negative voltage is applied to the gate electrodes 8, the device is in an "off" state. Under the circumstances, if a high voltage is applied across the source electrodes 11 and the drain electrodes 12, a depletion layer grows from a p-n junction defined by the n.sup.- -type semiconductor island 1 and the p-type diffusion regions 5, so that an almost entire region of the n.sup.- -type semiconductor island 1 is depleted. Thus, high breakdown voltage characteristics of the device can be implemented. On the contrary, when a positive voltage is applied to the gate electrodes 8, portions of the p-type diffusion regions 5 beneath the gate electrodes 8 are inverted into n-type to form channels, through which electrons start flowing. The electrons reach the n.sup.+ -type semiconductor layer 2 via the n.sup.- -type semiconductor island 1, and further reach the drain electrodes 12 via the n-type diffusion region 9 and the n.sup.+ -type diffusion regions 10, thereby turning the VDMOS transistor to an "on" state.
With a conventional semiconductor device comprising as the above, if the n.sup.- -type semiconductor island 1 has a large surface area, current is extracted using the n-type diffusion region 9 located in the center of the island as well as the n.sup.+ -type diffusion regions 10 in the island edges in avoidance of an increased product of ON-resistance multiplied by area. When the n.sup.- -type semiconductor island 1 is thick, the n-type diffusion region 9 in the island center must be deeply diffused. This unavoidablly results in increase of lateral diffusion, which causes a trouble of the n-type diffusion region 9 occupying an unnecessarily large surface area.